PJ FET High Side Voltage

High side FET drive on the PJ inverters is actually quite high at 18v...leaving only 2v headroom to the absolute max of 20v on the newer FETs.  Makes it very easy for induced EMI or ring in the cable to damage the FET gates, causing random FET failure for seemingly no reason at all.  Low side FET drive is actually the lower drive voltage...and due to a rogue LED, one side gets 10v signal, and the other 12v.  Good grief...

The heat on FETs in a PJ inverter is actually due to the LF driver being far too weak to cleanly switch the FETs--if you take a 'scope to the gate drive waveforms, the corners are rounded (= more time spent in the "resistive" part, instead of fully on or fully off.)  Double mainboards are double the trouble, with double the load on an overloaded driver...making the problem considerably worse.

Worse, because the high side and low side drivers are mismatched, it turns out that the dead-time setting in the CPU is too short.  I actually reduced the no-load consumption of a PJ inverter by increasing the CPU's dead time setting.

Yes, these problems are completely remedied on GS inverters.  At no load, FETs stay cold (or barely warm).  Transformer is practically silent.  And the ferrite choke gets HOT (due to the clean output from the firmly driven FETs).  I am planning to produce an "improved LF Driver" for PJ inverters that balances the drive voltages and drive methods; however, without upgraded code in the CPU, there's still a lot to be desired.

How is the high side gate voltage generated? Is it all just a bootstrap charge pump? Seems like with a bunch of FETs that technique would be maxed out pretty quick.

I ask for a selfish reason. I have a load I'm going to switch with an N-channel Mosfet on the high side. Because it is what I have on hand and the ground needs to be continuous. I won't be using a driver IC. But I'm having a little trouble on the control side. So I'm fishing for how it is done in the big inverters.

Bootstrap is only viable if you have a half-bridge setup and a high enough frequency to keep the flying cap charged.  For a single high side FET--and especially for 100% duty cycle situations, you'll need an isolated power supply.  Which is basically the PJ method.

You'll need the following parts:

• an isolated DC-DC converter for the "floating" supply
  • 12v output should be adequate, particularly if you're just doing a "switch".  Can search eBay for "NME1212", or dig around a bit--this assuming you have a 12v input to the control circuitry.
  • 15v output won't hurt at all, and will ensure the FET is fully on.  If you're at 5v power input, try ROE-0515S .  12v...well you get the idea ("1215" converter)
  • These converters get rebranded a lot, so you should be able to find what you need.
• a driver IC (yes, you'll need one).  If you're using 1-2 FETs, the TLP350 opto-driver used on the PJ LF drivers will be quite adequate.

Ok, so I'll elaborate now that you're here😀 This load will often be just fully on. But it will also often be PWM'd by a controller that uses 12 volt drive. I haven't looked inside it and have no specs other than it is 24 V input, 12 V signal output, and 20 kHz PWM. I have built two circuits that turn on the FET effectively. Very sharp rise and fall during switching. They both work well driven by my signal generator. 

The circuit in the pic is the most efficient of the two I breadboarded. This pic is a screenshot of EveryCircuit circuit simulator. It doesn't allow me to add labels. I apologize. I built this circuit and it works fine. The FET goes all the way off very sharply all the way through the frequency I expect it to operate on. The heat sink doesn't even get warm under full load or rapid PWM.

BUT! When the signal line is open, my FET drive circuit signal input goes to 36 volts, which is the gate drive supply voltage relative to ground. And I don't really understand why that voltage appears at the signal input which would be the base of the bottom left transistor. So I'm afraid to connect it to the existing controller without getting a handle on what, exactly, is happening. When I turn the FET on with a hard 12 V signal, the line obviously goes to 12 V. But once open, it hits the gate supply voltage of 36 V. It's even 36 volts with a smaller pull down than 100 k. I can use up to 330k resistor in line with the signal and still effectively trigger the FET. The way I'm thinking, with the first transistor from the left off, the second transistor should be pulled up and on, so the voltage at the base of that transistor (and collector of the first transistor) should be 1 base-emitter voltage drop, not 36 V.

At 330k, 36 volts could only push 1/10 mA max. So my gut feeling is that the 36 volts on the open signal line is harmless and won't source enough current to damage the driving device. But I think I need some guidance on analysis of this circuit, specifically at the input side. By the way, I'm representing the driving device as the switch and 12 V source on the lower left side. The gate drive supply is in the upper right.

First of all, your gate drive power source MUST be referenced to the source, not the drain of the FET.  This probably why you're getting 36v on the gate, because the power supplies are stacking.

Secondly, I am NOT a fan of the totem-pole gate driver method (which PJ uses for the low-side FETs).  Just a personal thing I guess...because it will have different drive characteristics than the high-side driver (if applicable).  Nothing wrong with it otherwise.

Thirdly, you can literally replace your entire circuit with a TLP350 removed from a PJ LF Driver (if you have extras).  All you need to drive the FET is a TLP350, a gate resistor, and your gate drive power source.  That's literally it.  (EDIT: and a ceramic filter cap right on the '350)

The input signal being 12v will need a suitable resistor (4.7k should be fine) into the LED on the TLP350, and you'll be completely set and done.

Try this.

The 100nF capacitor on the output of the TLP350 needs to physically very close to the chip, preferably a ceramic cap (not an electrolytic).

Gate resistor...you may need to play with this value to prevent ring and overshoot of the FET gate.

TLP350...if this is a single FET and you need to buy parts anyway, you can probably use a TLP250 (lower amperage).

Thanks Sid! Buying stuff isn't nearly as fun. This isn't a project that I'm passionate enough about to spend money on. But is now more of a curiosity and learning exercise. I understand that the gate power supply is in series with the main supply giving 36 volts relative to ground. How would that be different than using a separate 36 volt supply referenced to ground? I have seen circuits that used a higher voltage ground referenced supply to drive a high side FET. I thought this would be effectively the same thing. 

In my circuit, the Vgs never rose above 12 volts (some tiny 14 volt peaks when rapidly switching). At any rate, I appreciate the feedback. Since it is a single FET, I'm going to rearrange the circuit to reference the source directly.

In my mind, I thought a single "drain referenced" supply would effectively be a 36 volt relative-to-ground supply and could be used to switch different high side FETs at different times.

So when driving a high-side fet, "reference to ground" is of absolutely no value.  What matters is "reference to the source", which is why your floating isolated supply must be referenced to the source of the FET.  A 0v potential between G-S means the FET is off.  A 12v potential between G-S means the FET is fully on.

In most cases, a high-side driver will not have a connection to the drain of the FET; if there is a connection, it's usually for short-circuit (or other fault) detection.

Running a 12v supply in series with your 24v supply...if the FET is off, and the Source is at +24v, then yes, you will happen to have +12v above the Source to turn the FET on.  But as soon as the FET turns on and sinks down to 0v (or thereabouts, that 1-ohm resistor will drop a few volts), now your series +12v supply is towering some 30v over the FET...which is quite beyond the absolute max G-S voltage of 20v (or 25v if you're lucky, check the datasheet).

This is why the floating supply needs referenced to the Source of the FET.  No matter where the FET is with respect to the "other" supply rail, you can always get the +12v on and 0v off signals to the gate.  Basically you can put the +12v supply across the totem-pole transistor drivers.

I am more confused. Surprise, surprise. If the FET is off, the source should be at 0 volts because it is pulled down through the 1 ohm load. And if the FET is on, the source should be at nearly 24 volts because almost no voltage is dropped across the fet and all across the load and the Vgs should be 12 volts. Which is opposite of what you said. Did you mis-type that or am I really just missing the mark by that much?

Im not trying to annoy, just trying to understand. You design inverters. I occasionally burn myself with a soldering iron. I know my place😂

16 minutes ago, InPhase said:

If the FET is off, the source should be at 0 volts because it is pulled down through the 1 ohm load. And if the FET is on, the source should be at nearly 24 volts because almost no voltage is dropped across the fet and all across the load and the Vgs should be 12 volts. Which is opposite of what you said. Did you mis-type that or am I really just missing the mark by that much?

Ha, you're right...I completely got that backwards 🤣...

Still, the floating 12v supply should be referenced to the Source of the FET, not the drain.

Thanks Sid. You're alright, no matter what Ben in West Virginia says about you.

You mentioned not liking totem poles. What's a better discrete-component alternative to the totem pole for getting a clean sharp rise and fall?

Nothing that I'm aware of 🤣.  They probably work great (never used 'em myself)...just in an full-bridge or half-bridge FET setup, it's a bad idea to mix different types of FET drivers due to the completely different characteristics that will be encountered.  Kinda like mixing short and tall people...they can do the same work, just slightly differently, and might not work together super well. 

In your case with a single high-side FET, it probably works swell.

Actually, if you look at the schematic symbol for the TLP350, it's got a totem-pole output driver...