More MOSFET Explosions

Groan....more than I care to admit 🤯.  Blew through nearly 200pcs trying to figure out a frustratingly precise explosion at 3kw on a 12kw test prototype (different FETs than the ones that work well).  Turned out that my 0603 gate resistors were...a little undersized, and were blowing open-circuit, leaving the FETs to basically kill themselves across the battery...

Very first set of FETs I blew up was thanks to the ridiculous 'scope grounding rule--grounding the probes.  Touched the probe negative to the high-side FET gate (by accident), and *poof* there went the FETs.  Next step was to rip the ground prong out of the 'scope power cord....

Getting a bit cobbled there...but I think I see why.  Doesn't look like the ATMega328 has any proviso for motor drive PWM (i.e. complementary outputs, dead-time settings, or PWM shutdown)...so it appears to me that you're using the IRF21844 chips for their complementary output design and dead-time functionality (i.e. the functionality that the ATMega328 doesn't have).  And then tagging the TLP351s on the end of the whole thing...

Worth noting that the GS boards literally feed the MCU's SPWM outputs directly into FET drivers (same design concept as the TLP351, though rated at 4A instead of 0.6A), and directly out to the FETs.   Lot simpler....but the GS MCUs also have full complementary PWM outputs, dead-time and hardware PWM shutdown capabilities built-in.

IRFB7545 = 55v...IRF3205 = 60v...

What's your DC bus voltage here?  I'm assuming you're shooting for 24v...because those FET voltages are too low for 48v 😉.

Other thoughts:

• What's your dead-time delay? ("programmable" on the IR21844 chips w/ a resistor)
  • if it's too small, you'll obviously have possible cross-conduction across the H-bridge
  • if it's too large, the transformer will have time to start to "kick" back (particularly with inductive loads).  This does become problematic...
    • the body diodes on the FETs are NOT ultra-fast recovery (i.e. <35nS).  This means that they MAY not switch fast enough to clamp a transformer kick-back, depending on the dv/dt of the spike.  (Datasheet on the IRF3205 indicates 69-104nS reverse recovery time for the body diode.)
    • the longer the H-bridge is "open", the more opportunity for an unclamped kick to damage the FETs.
• What capacitors are you using for DC bus filters?  (particularly important is the ESR rating)
  • if they're too small and/or have too high of an ESR, they won't be able to absorb transformer kicks/spikes--and the FETs will be damaged through overvoltage.  This is even if (and especially if) the FET body diodes are gating transformer kick back to the battery rail.
  • these capacitors' main function is absorbing spikes and preventing the battery cables from turning into giant inductors.
• Is the SPWM H-bridge methodology top-down (a la PJ), where the transformer is clamped to battery positive and pulled to ground?  Or is it bottom-up (transformer clamped to battery negative and pulled to positive)?
  • this only affects which side of the H-bridge is most likely to be problematic
• Do you have any ferrites / E-cores between the FETs and the transformer?

I presume you are checking BOTH high and low sides (though not simultaneously)...at no load as well as under load?

Transformer impedance and behavior changes CONSIDERABLY from no-load to loaded--this is why it's important to 'scope the gate signals under load.  Basically all of my smoked FET tests looked beautiful at no-load (or even small loads).  It generally isn't until 3-6kw that the gremlins really start to show.

Frankly, these are significantly over-rated 😉.  If you have any sort of dangerous transients on the FETs, you need to reduce the switching dead-time.  A little 100nF capacitor against a giant transformer...is like trying to use an ant to hold back a falling boulder.

Have you 'scoped the drain-source on both the low and high-side FETs as well?  Under load?  I'm assuming you have a DSO (digital storage scope)--they might well be dubbed "Nintendo scopes", but are VERY handy for capturing and examining waveforms up close.

My scope is just a cheapo USB oscilloscope that's good to 20 MHz but it doesn't store anything. I don't know the ESR of the caps but there is a 1 uF MLCC cap in parallel. 24 volts is my battery voltage. The transformer goes to ground when not being switched. I have a 100 uH choke before the transformer and a 2 uF polyester cap on the secondary. The dead time is approximately 500 ns.

The 21844 chips are used as you guessed, to provide dead time. I wanted to use a cheap and widely available uC for the SPWM as well as for modularity. I found a project on the AnotherPower forum and followed it to The Back Shed forum. A nice implementation of SPWM on Arduino. Originally the 21844s used a bootstrap circuit to drive the high side FETs but through experimentation I found it stupid easy to destroy them and/or the Nano, so I inserted the TLP351 to provide some optical isolation. I had some small 15 watt isolated 12 volt power supplies laying around and used them for high side gate supply. I have not looked at what is happening between the source-drain... I haven't had enough time before sending the FETs to transistor heaven. When the FETs blow they often go shorted between gate and drain and the TLP351 dies too if I don't kill the power soon enough.

Hmm...unless you can prove otherwise via your 'scope, this might be a little too low.  Remember, transformer inductance/behavior changes CONSIDERABLY between no-load vs loaded--so just because it works at no load doesn't necessarily indicate that everything's kosher.  All it takes is the transformer pulling a bit harder--increasing the FET "pull down" time, and you can easily have an H-bridge cross-conduction event.  If one there's one thing those DC bus filter caps have (assuming they're sizeable), it's enough power to fry FETs instantly!

GS inverters run closer to 2uS dead time; for software debugging, I hard-limited the dead-time at no less than 500nS--as the no-load current starts to notably increase as the dead-time is reduced much below 1uS (due to cross-conduction). 

The longer the dead-time, the more "buzzing" noise you'll get in the transformer (as the transformer's kickback is allowed to "build" before the FETs clamp it).  The shorter the dead-time, the quieter the transformer will get...until H-bridge cross-conduction starts to increase no-load current.  (You should easily be able to see the dead-time on your 'scope when observing drain-source and/or the transformer primary.)

Can you zero in on parts of the waveform and/or "freeze" the view?

I personally misunderstood what was meant by a "storage" scope for the longest time.  I currently have a Siglent SDS1104-X...and "storage" seems to simply mean that I can hit the "Stop" button and it'll "freeze" what's on the screen.  Depending on the capture depth, I can then zoom in and examine things a bit closer, etc.

If you were only using a single FET per quadrant...your FETs have a 25C continuous rating of ~90A.  At 24v, that's barely 2kw without considering inefficiencies.  (It's worth noting that the "pulsed drain current" rating of 300A+ is more or less useless for calculating "inverter surge"--as said rating is usually specced at 100uS, not the 250mS an AC startup surge can easily run to!)  I personally prefer to calculate FET maximums by using their 100C rating, as that gives a solid safety margin regardless of FET temperature.  (Which for the IRFB7545 is all of 67A...and if you had 2 per quadrant, that's 67 * 2 = 134A * 24v = just over 3kw.)

If all measurements (under load) look clean and good, and the dead time isn't too low...you might just need more parallel FETs.  But if it blew out with a 250W light bulb, then there's probably something fishy going on with the FET signals.

So a negative-based control (same as the GS inverters due to the boostrap requirements)...and funnily enough, makes those low side FETs quite a trouble 😉.

I'm now convinced that the biggest problem is the propagation delay across the opto drivers. I thought it would be a super rugged design to drive each FET individually, but I didn't fully read the datasheet. It makes sense with the failures I've seen. The first failure was just a huge current from a stalled motor going through single FETs. The next failure was similar. That latest failure with the 250 watt lamp was the first time I ran with parallels FETs and individual drivers. And the low side FETs popped in rapid sequence like fireworks. I think I'll fall back and punt. My perfboard prototype was just parallel FETs switched by a BJT totem pole and it never blew up. I'm thinking that should do the trick.

What do you think of this FET from Toshiba:  https://www.mouser.com/datasheet/2/408/TK3R2E06PL_datasheet_en_20210120-2509708.pdf

At least so far as I've seen, BJTs are CONSIDERABLY slower than FETs.  (This could become quite problematic if Miller spikes are an issue; at 24v, you likely won't have a serious issue with them.) 

The TLP351 has a propagation delay time of <1uS--I will be surprised if you can match that speed with BJTs of any significant size.

Also worth noting is that with the fully isolated opto-drivers, they become the "failure end" point--in GS inverters, damage never once has traveled upstream from the opto-drivers to the CPU.

However, seeing up to 700nS listed on propagation times PLUS a variance of up to 1uS...yeah, your dead-time at 500nS is way too short 😉.  You need a longer dead-time...totem pole BJT or not.

Whoa, really like that Rds(on) of 2.4mOhm...

...gate capacitance isn't too bad (5000pF), reverse transfer is OK at 55pF...

...switching speed is EXTREMELY fast at 32nS total on, 82nS total off...good luck finding a BJT that's anywhere close to THAT!

Looks like a solid FET to me.

EDIT: You might be able to get an even lower Rds(on) if you drop to 40v FETs.  For a 24v system, 40v FETs should be decently adequate.

Does the BJT speed matter if there is only one totem pole per set of parallel FETs? The propagation delay of the TLPs is significant because parallel FETs on the same quadrant are turning one and off at slightly different times. But if I use one BJT complementary push-pull setup, there's only one drive signal per quadrant. 

Blew through nearly 200pcs trying to figure out a frustratingly precise explosion at 3kw on a 12kw test prototype 

Ebay has the good FETs  back in stock  for 100  dollars .   

5 hours ago, dickson said:

Blew through nearly 200pcs trying to figure out a frustratingly precise explosion at 3kw on a 12kw test prototype 

Ebay has the good FETs  back in stock  for 100  dollars .   

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Why are these good FETs? I have had terrible luck in the past with counterfeit stuff on Ebay. 

12 hours ago, InPhase said:

Does the BJT speed matter if there is only one totem pole per set of parallel FETs? The propagation delay of the TLPs is significant because parallel FETs on the same quadrant are turning one and off at slightly different times. But if I use one BJT complementary push-pull setup, there's only one drive signal per quadrant. 

Why do you need separate TLP351s for each FET?  You could just as easily use a single TLP350 (2.5A) per quadrant...or if you can find it, a TLP358 (6.0A).

EDIT: there's also TLP352 (2.5A), and TLP700 (2.5A).

TLP352 has a propagation delay of 200nS, error +/-80nS.  Considerably better than the TLP351 (at 700ns, error +/-500nS) or the TLP350 at 500nS max.

Why are these good FETs? I have had terrible luck in the past with counterfeit stuff on Ebay.

Sean say in his youtube  that NCEP039N10  is a  good  FETs .     I  always check  all the FETs  in diode mode  and check all the resisters  before  using .   I  do find  bad FETs  on  some mosboard  and  bad resisters  also .    I  had  over one hundreds  FETs  blow up  but now I  stop trying to make a better PJ  inverter .    

I don't NEED one per FET. The story is something like this: I made a MOSFET module for general purpose switching of heavy DC loads. I wanted a single replaceable module to use across my various pumps and lights and fans, etc. at my off grid cabin. It worked so well and reliably that I made another module that could take a TLP style opto driver to use in PWM high side projects. It can take a bipolar or bipolar gate supply. And THAT worked so well that I thought I could make a modular inverter power board based on the same footprint. Furthermore, being ignorant of the propagation variance, I thought driving each FET would be a tough dependable topology. Knowing what I know know, I'm going to regroup and and think of something else. 

A much simpler proof-of-concept design would be to increase the dead-time to 1uS+ and see if that helps.  If it's too long, the transformer will start to get "buzzier."  If it has been too small, your no-load current will decrease as you increase the dead-time.