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no when I put them in the slave with the other three fets still in the slave, it never went into inverter mode. so luckly it didn't. I just put the one fet board and driver board back into the master as it was and its back the way it was, just with the input and output terminal hot with a meter all the terminals are litterly join, no matter which combinationRe you test them it beeps. and with a fan plugged into the outlet its comes on, then off, on and off:
But, the fets are working.
when I tested the slave, terminals I get beeps on all of them but one don'ts beep one of the input , I think its the leg input don't test to the othe two output leg outs. just the common makes it beep. since I'm guessin the common on the input and output are tied as one.
@notmario Yeah, well. Sid basicly says to replace them all, because of something like your saying could be the case. and for me to find it would be like asking a person to get out of a salt mine with no light source :P.
If the little board that is on the control board that can be removed, yeah it blown it. I've been kind of scratching my head on how the fet board system works. I'm guessing the heat sink conductive? and the six small screws are going to six different channels? I didn't noticed until last time I was looking that there is four heat sinks, I thought it was two big ones. Its pretty intresting how this stuff works.
I would imagine it would be quite difficult without sight. I wouldn't advise being unnecessarily cheap like myself and risking further damage - but since you seemed eager to turn it on, i figured i'd at least give you a way to reduce the risk.
So basically (the way i think it works...) the backside of the fets (the drain) are conductive to the heatsink. For each board, a single riser is used to drive ALL the fets. (kind of like the starter solenoid on a car) The other risers supply the power for the source. The driver board supplies power to the gate risers for each fet board independently in a binary pattern that approximates an AC wave. When the gates are driven, the fets short the source to the drain - which basically alternates the connection between the DC source and the transformer primaries. Which fet board is activated (gate driven) dictates which polarity reaches which part of the transformer.
You can kind of think of the driving process as a series of pulses dictating the polarity (or 0v) to the transformer primaries. A sequence like 11211211212221211211211,11011011010001011011011 ("AC positive", "AC negative") kind of describes a ternary representation of the rise and fall of an analog AC wave - where 1 would be the "no DC" (no fets driven), 2 would be "positive DC", and 0 would be "negative DC" to the transformer primaries. Of course the inverter generates a much more granular sequence - with many thousands of numbers representing just one wave.
You can imagine how a fet that has failed closed would be an issue - two fet boards would essentially be shorting both + and - to the same transformer lead.
So basic the heat sinks are DC driven, but switch on and off by the control board telling the main board to send the pulses to each riser in a pattern that represents the ups and down of the AC wave that is generated by the coil being fed the DC current on and off through each of its windings. Hence I'm guessing since mine is a 24v system each heat sink seems to have two primaries' which almost tells me each one is a 12v x 2 = 24v winding. 2 sets of negative and 2 sets of positive? have not went back to check if that is the case, but seems as such. I noticed that the positive terminal goes directly to the heat sink, yet the negative terminal is going to the main board, so I'm guessing the main board is the gate way to turning on and off the negative side to incite the coil to generate the AC wave.
So basic the heat sinks are DC driven, but switch on and off by the control board telling the main board to send the pulses to each riser in a pattern that represents the ups and down of the AC wave that is generated by the coil being fed the DC current on and off through each of its windings. Hence I'm guessing since mine is a 24v system each heat sink seems to have two primaries' which almost tells me each one is a 12v x 2 = 24v winding. 2 sets of negative and 2 sets of positive? have not went back to check if that is the case, but seems as such. I noticed that the positive terminal goes directly to the heat sink, yet the negative terminal is going to the main board, so I'm guessing the main board is the gate way to turning on and off the negative side to incite the coil to generate the AC wave.
You've got the right idea.
So, as for the transformer. I'm not sure the exact configuration of it (so these numbers are just examples), but think of it like it has 4 sets of primaries. You can put those primaries in any combination of series and parallel. Put all of them in parallel [1S4P] you have a ratio of something like 1:20 (12v -> 240v). Put two pairs in parallel, then put those pairs in series [2S2P], you'll get 2:20 (24v -> 240v). Put all the primaries in series (4S1P), you'll end up with a 4:20 ratio (48v -> 240v).
There are also 2 secondary windings. In a split phase system, you put them in series, for the total of 240v with 120v to center tap. In a 120v system, you put them in parallel, splitting the ratio in half thus halving the voltage to 120v, but with double the maximum amperage.
As for how the + and - wires are connected ... yes, + goes to the big heat sink, and - goes to the mainboard. This appears to be a design choice, and it's a little beyond me the exact reasons it's done this way - but i suspect this design permits universalizing the fetboards so you don't have to have 2 different types). But that's just a guess.
Yep, well mine is setup as a 120v system with two 120v in the same phase.
This appears to be a design choice, and it's a little beyond me the exact reasons it's done this way
So in a FET H-bridge, the high-side FET drain leads go to battery positive. It just so happens that the drain lead in a TO-220 MOSFET is directly tied to the heatsink tab--making it a VERY convenient mounting post! On the low-side FETs, the source leads go to battery negative--and the source lead isn't the heatsink tab, so we have to connect that on the PCB.
Transformer lines connect to the low-side FET heatsinks--again, because the heatsinks are the low-side FET drain leads. Just a matter of convenience.
You can kind of think of the driving process as a series of pulses dictating the polarity (or 0v) to the transformer primaries. A sequence like 11211211212221211211211,11011011010001011011011 ("AC positive", "AC negative") kind of describes a ternary representation of the rise and fall of an analog AC wave - where 1 would be the "no DC" (no fets driven), 2 would be "positive DC", and 0 would be "negative DC" to the transformer primaries. Of course the inverter generates a much more granular sequence - with many thousands of numbers representing just one wave.
Actually in normal "inverter" mode, there's (basically) never a time when the FETs aren't either shorting the transformer across the battery, or shorting the transformer out. It's sort of like a Class-D amplifier in that regard--and that's why the chokes are so important on the transformer lines! It might seem that "letting the transformer free" might notably reduce no-load--but it doesn't (I've tried!) What it does do is result in an AC wave that looks like it might fall over--and that was at no load. Loads without a perfect power factor would run the AC wave into an absolute mess, as the inverter would have no way to hold the wave in shape.
Well, I would like to get my two gs back up and going, my power bill has sky rocketed, as I was useing the GS to keep my power bill at half cost. The phone number and leaving a voice mail only one time last week, and no way to order any sepaerate parts on the web site. . . I don't want to bug Sid, he is over worked. . . .
Actually in normal "inverter" mode, there's (basically) never a time when the FETs aren't either shorting the transformer across the battery, or shorting the transformer out. It's sort of like a Class-D amplifier in that regard--and that's why the chokes are so important on the transformer lines! It might seem that "letting the transformer free" might notably reduce no-load--but it doesn't (I've tried!) What it does do is result in an AC wave that looks like it might fall over--and that was at no load. Loads without a perfect power factor would run the AC wave into an absolute mess, as the inverter would have no way to hold the wave in shape.
And this is why i don't build my own inverters. 😉 There's a lot more to it than i understand.
Do explain to me though. You're saying the [what i'm calling] "0v state" isn't simply an open link - but instead the fets are actually shorting the primary windings? That's quite interesting - that would basically cause the winding to briefly resist the magnetic field collapsing.
So in a FET H-bridge, the high-side FET drain leads go to battery positive. It just so happens that the drain lead in a TO-220 MOSFET is directly tied to the heatsink tab--making it a VERY convenient mounting post! On the low-side FETs, the source leads go to battery negative--and the source lead isn't the heatsink tab, so we have to connect that on the PCB.
Transformer lines connect to the low-side FET heatsinks--again, because the heatsinks are the low-side FET drain leads. Just a matter of convenience.
This was basically what i was thinking. Otherwise, as i understand, you'd have to basically connect half the source-leads to a DC-negative heat sink, then put the transformer leads on the mainboard(?) - but of course that would require weird fets that connect the source to the heatsink tab, which would require 2 types of fetboards.
but of course that would require weird fets that connect the source to the heatsink tab, which would require 2 types of fetboards.
Bigger problem being that every N-channel FET that I'm aware of has the heatsink tab (if present) connected to the drain connection. I'm suspecting that likely has something to do with the actual MOSFET design topology, but don't know for sure.
then put the transformer leads on the mainboard(?)
Technically the transformer leads could be bolted to the "source" screws of the high-side FET boards ;-). Just a lot less convenient from a logistical perspective.
Do explain to me though. You're saying the [what i'm calling] "0v state" isn't simply an open link - but instead the fets are actually shorting the primary windings? That's quite interesting - that would basically cause the winding to briefly resist the magnetic field collapsing.
Correct: at the zero crossing, both low-side FETs are active, shorting the transformer primary winding. This is actually partially why backfeeding the inverter can be so fatal: at 0% throttle (i.e. soft-start startup), the low-side FETs are basically holding the transformer primary in a dead short. If it's got full AC mains power behind it, *poof* go the FETs due to brute overcurrent.
Plus due to the intrinsic body diode in the FETs, even if one half of the bridge is switching at something higher than 0%, out-of-phase backfeed (which due to Murphy's Law is most of the time) gets gated through the low-side FET body diode--same result anyway I guess!
But the FETs "forcing" the transformer waveform is largely how the inverter can maintain a fairly decent sine wave regardless of the load. (Distortion in the sine would be a factor of the DC power path resistance, i.e. batteries -> cables -> FETs -> transformer primary.)
Worth noting: parallel and hybrid power sharing modes will "freewheel" the transformer (i.e. not short it out, the SPWM doesn't drive the low-side FET). That way a 0% throttle (SYNCED to input!) doesn't short out the AC wave...which is kinda critical for FET survival! It won't be able to maintain the AC wave shape (as that's the "input" power source's responsibility), but it will be able to "push" power back the other way. (Been tested.)
Correct: at the zero crossing, both low-side FETs are active, shorting the transformer primary winding. This is actually partially why backfeeding the inverter can be so fatal: at 0% throttle (i.e. soft-start startup), the low-side FETs are basically holding the transformer primary in a dead short. If it's got full AC mains power behind it, *poof* go the FETs due to brute overcurrent.
Yeah, and there's no current limiting on that side of the mainboard to save them.
Worth noting: parallel and hybrid power sharing modes will "freewheel" the transformer (i.e. not short it out, the SPWM doesn't drive the low-side FET). That way a 0% throttle (SYNCED to input!) doesn't short out the AC wave...which is kinda critical for FET survival! It won't be able to maintain the AC wave shape (as that's the "input" power source's responsibility), but it will be able to "push" power back the other way. (Been tested.)
Yes, that makes sense - closing the primary would just leech power when power is available on the secondary.
Very interesting information. One of these days i'll have to play around with a powerjack build - drive the fets with my own programming.
Yeah, and there's no current limiting on that side of the mainboard to save them.
Correct...the current limit on the all-original GS inverters is on the negative power feed to the mainboard--not between the low-side FETs. Starts to get a bit complicated there!
The heatsink is always on drain because that's the back of the wafer
A fet that has been over current or voltage will often have damage to it's ability to isolate the gate
This will cause performance issues and decay into a short even if the damage isn't notable
Because when the fet does go it shorts all 3 pins but often burns off the source pin, the gate gets hit with battery+ burning the driver board
the gate gets hit with battery+ burning the driver board
Bingo 🤣 . I put TVS diodes on the new GS FET boards to hopefully prevent that--but it's not improbable that the TVS diodes will vaporize as well.
The heatsink is always on drain because that's the back of the wafer
That's what I thought. But I didn't make that argument because I was unable to find any MOSFET wafer diagrams online to corroborate that. Maybe you have some docs/diagrams?
The heatsink is always on drain because that's the back of the wafer
That's what I thought. But I didn't make that argument because I was unable to find any MOSFET wafer diagrams online to corroborate that. Maybe you have some docs/diagrams?
FYI, that's why i described them as "weird fets". All that to say it was designed that way for good reason. 😀
Well, I know I need fet boards and a driver board. sucks my power bill was normaly running 8 to 15kw a day, now its hitting nearly 41kw since I went down. If I knew I could get by with one GS if I could switch it to 240v mode I would get my master back up and running, but since my two GS are setup as a 120v only no dice. and I'm not going to even bother with swapping wires around, since sid is booked. I actually could run my whole house off of one GS, well sort of, wouldn't be able to run a induction or microwave while the AC is running unless I unlock the GS .
the gate gets hit with battery+ burning the driver board
Bingo 🤣 . I put TVS diodes on the new GS FET boards to hopefully prevent that--but it's not improbable that the TVS diodes will vaporize as well.
Wait, TVS Diodes? Using your TV as a parts experiment? That's a Real Dedication there. No wonder you don't watch TV. . .
The heatsink is always on drain because that's the back of the wafer
So basicly the one leg of the fet is basicly the back side of the fet and the risers are the other leg of the fet? thats intresting.